1) Field of the Invention
The present invention relates to a cache memory device having an n-way set-associative cache memory and to a memory allocation method. More particularly, the invention relates to a cache memory device and a memory allocation method capable of uniquely specifying a way in which an error occurs and changing the number of ways without degrading performance of the device.
2) Description of the Related Art
FIG. 7 is a block diagram showing the configuration of a conventional cache memory device. The cache memory device shown in FIG. 7 comprises a multiple cache memory (a primary cache memory 12 and a secondary cache memory 14) to compensate for a difference in speed between a central processing unit (CPU) 10 and a main memory 15.
The CPU 10 accesses the primary cache memory 12, the secondary cache memory 14, or the main memory 15 to read/write data.
The main memory 15 has such characteristics that the main memory 15 has a large capacity and an access time is longer than that of the primary cache memory 12 and the secondary cache memory 14. The main memory 15 stores all data used in the CPU 10.
The primary cache memory 12 and the secondary cache memory 14 are, for example, static random access memories (SRAMs), and have such characteristics that an access time is shorter than that of the main memory 15.
The primary cache memory 12 has such a characteristic that the primary cache memory 12 has an access time shorter than that of the secondary cache memory 14. More specifically, of the primary cache memory 12, the secondary cache memory 14, and the main memory 15, the primary cache memory 12 has the shortest access time, the secondary cache memory 14 has the second shortest access time, and the main memory 15 has the longest access time.
In addition, in consideration of a storage capacity, the main memory 15 has the largest storage capacity, the secondary cache memory 14 has the second largest storage capacity, and the primary cache memory 12 has the smallest storage capacity.
In this case, data transfer between the CPU and the cache memory (main memory) is performed in units of lines. Some schemes that correlate data on the main memory with the lines in the cache memory are known.
As a typical scheme, there is a set associative scheme. This scheme divides a main memory and a cache memory into a plurality of sets (sets of lines: which are called ways), and allows data on the main memory to be placed only on a predetermined line in the respective ways.
The set associative scheme is referred to as a direct mapping scheme (or a one-way set associative scheme) when a cache memory is handled as one way, and is referred to as an n-way set associative scheme when N ways are used.
FIG. 8 is a diagram for explaining the correspondence between the main memory 15 and the secondary cache memory 14 with respect to the direct mapping scheme. In FIG. 8, 5-bit addresses and data are (data 0 to 4, . . . ) are stored in the main memory 15 so that each of the addresses is paired with each of the data.
The secondary cache memory 14, as shown in FIG. 7, comprises a secondary tag RAM 14a and a secondary data RAM 14b. In the secondary cache memory 14, the lower two bits of each address stored in the main memory 15 are stored as an index in an “index”.
The upper three bits of each address stored in the main memory 15 are stored as a tag in a “tag”. These “index” and “tag” are stored in the secondary tag RAM 14a (see FIG. 7).
On the other hand, data stored in the main memory 15 are stored in “data”. The “data” is stored in the secondary data RAM 14b. 
In contrast to this, FIG. 9 is a diagram for explaining the n-way set associative scheme in the secondary cache memory 14. In FIG. 9, the secondary cache memory 14 is divided into n WAYs and managed, and the WAYs of the secondary tag RAM 14a (see FIG. 7) and the WAYs of the secondary data RAM 14b have one-to-one correspondence.
In FIG. 9, in the same manner as that in FIG. 8, the upper three bits of each address stored in the main memory 15 are stored as a tag in the “tag” of the secondary cache memory 14. These “index” and “tag” are stored in the secondary tag RAM 14a (see FIG. 7).
On the other hand, data stored in the main memory 15 are stored in the “data”. The “data” is stored in the secondary data RAM 14b. In the following description, it is assumed that the secondary cache memory 14 is an n-way (4-way) set associative cache memory.
Returning to FIG. 7, the primary cache memory 12 stores some of the data stored in the main memory 15, and is a an n-way set associative memory. This primary cache memory 12 comprises a primary tag RAM 12a and a primary data RAM 12b. 
In a conventional cache memory device, each of a primary cache access controller 11 and a secondary cache access controller 13 has a function of correcting error data into correct data by using tag management data 20 shown in FIG. 10.
The tag management data 20 is stored in the primary tag RAM 12a or the secondary tag RAM 14a, and comprises a tag 21, a tag 22, and an error checking code (ECC) 23.
The tag 21 corresponds to a WAY m. The tag 22 corresponds to a WAY n different from the WAY m of the tag 21.
The ECC 23 is redundant data added to the tag 21 and the tag 22. The ECC 23 is an error correction code used to correct error data into correct data when an error occurs in any one of the tag 21 and the tag 22.
In the conventional cache memory device, there is a case, for example, where the secondary cache memory 14 of the 4-way set associative scheme shown in FIG. 11A may be changed into a secondary cache memory of a 2-way set associative scheme, i.e., the number of ways may be changed with a change in design or a change in specification.
In this case, as shown in FIG. 11B, the following changing method is employed. That is, the functions of WAY 2 and WAY 4 are stopped (e.g., tags and data are deleted), and only WAY 0 and WAY 1 are functioned.
As described above, the conventional cache memory device uses the tag management data 20 that shares one ECC 23 for the tag 21 (WAY m) and the tag 22 (WAY n) of different ways, as shown in FIG. 10. Therefore, when an error has occurred, it is understood only that the error has occurred in either one of the WAY m and the WAY n. Therefore, the way in which the error has occurred cannot be uniquely specified.
Further, in the conventional cache memory device, as shown in FIG. 11B, the functions of WAY 2 and WAY 4 are simply stopped to update the number of ways. Therefore, the cache capacity of the secondary cache memory 14 becomes half, and the performance is degraded.